Increasing of capacity of a dynamic random access memory (DRAM) has been remarkably developed. In particular, in recent years, a layered DRAM in which a plurality of memory chips are layered has been proposed, and the capacity of the DRAM is further increased.
Meanwhile, in a case where a defect occurs in a portion of circuit components of the DRAM, a predetermined repair circuit (replacement circuit) is provided in the memory chip in order to repair the defective DRAM. For example, in a case where a defect is found in a word line (row) of the memory chip, another replacement word line is used instead of the defective word line. In addition, for example, in a case where a defect is found in a bit line (column) of the memory chip, another replacement bit line is used instead of the defective bit line. A word line or the like used instead thereof is an example of a repair circuit. A countermeasure against defects by providing a repair circuit in such a memory chip is similarly adopted in a layered DRAM.
FIGS. 8 and 9 are explanatory diagrams schematically illustrating a countermeasure against defects of a word line and a bit line in a layered DRAM 50 in the related art. In addition, in this specification, the term “layered DRAM” denotes a layered chip in which a plurality of semiconductor chips such as memory chips are layered or an electronic device as a DRAM provided with the layered chip.
FIG. 8 illustrates a state in which a plurality of semiconductor chips are layered to form the layered DRAM 50 (semiconductor chip) in the related art. As illustrated in the figure, the layered DRAM 50 in the related art is configured in which a plurality of memory chips CC0, CC1, CC2, and CC3 and one interface chip I/F are superimposed. In this figure, for the convenience of description, the number of memory chips CC is four, but other numbers may be used. The memory chip CC is a semiconductor chip including memory cells arranged on a matrix and circuits for controlling word lines, bit lines, and the like for the memory cells. The four memory chips CC0, CC1, CC2, and CC3 are functionally identical semiconductor chips. The interface chip I/F is a semiconductor chip including a logic circuit for controlling various signals between an external circuit and the memory chips CC. In addition, in this specification, the semiconductor chip may be simply referred to as a “chip”. As illustrated in FIG. 8, a memory chip (for example, CC0) constituting the layered DRAM 50 includes circuit blocks BK0 to BK15 in which memory cells are arranged and a peripheral circuit group 52 (illustrated by hatching in the figure) to transmit and receive signals with respect to word lines and bit lines in the circuit blocks BK0 to BK15.
FIG. 9 is a schematic plan diagram of one memory chip CC0. In the figure, in a case where it is detected that the word line WL in the circuit block BK0 is defective, a word line RWL which is a repair circuit is used instead as illustrated in the figure. In this manner, the process of replacing the word line WL with the word line RWL is realized by changing the allocation of the addressing in the peripheral circuit group 52 or the like. In FIG. 9, in a case where it is detected that the bit line YS in the circuit block BK9 is defective, illustrated is a state in which the bit line RYS which is a repair circuit is used instead. The process of replacing the bit line YS with the bit line RYS is also executed by the peripheral circuit group 52 similarly to the case of the word line.
In the layered DRAM 50 of the related art, as described above, repair circuits are provided for the respective memory chips CC0 to CC3, and in a case where a defect is found, the corresponding repair circuit is used instead. In this manner, in the layered DRAM, the production yield rate of the product is improved.